Achieving good detection performance while\nincurring low complexity is known to be one of\nthe major challenges in multiple-input multiple-output\n(MIMO) communications based on spatial multiplexing.\nThe tuple search detector (TSD) was recently introduced,\nimproving this trade-off with regard to other\ntree-search-based algorithms (e.g. single tree search or\nlist sphere detector). Motivated by the tremendous gain\nachievable through the turbo principle and based on a\npreviously developed soft-output (SO) TSD implementation,\nthis work presents the first soft-input soft-output\n(SISO) TSD realization, scalable in constellation size\nand number of antennas and mapped to a highly parallel\nand pipelined VLSI architecture. The proposed\nSISO-TSD VLSI realization is instantiated for 4 Ã?â?? 4\nMIMO transmission and 64-QAM constellation in 65-\nnm CMOS technology. For a given BER?complexity\ntrade-off, the throughput ranges from 57.3 Mbps (iterative\ndetection-decoding with 3 iterations) to 403.6\nMbps (non-iterative detection-decoding) at a clock frequency\nof 454 MHz. The BER?complexity trade-off\ncan be moreover adjusted according to transmission\nconditions, reaching >1 Gbps in high SNR scenarios.\nA silicon area of 0.14 mm2 (97.7 kGEs) is occupied\nby the SISO-TSD core, reporting low power dissipation\n(58.2 mW ââ?¬â?? 73.9 mW) under typical case operat ing conditions. The proposed detector implementation\nachieves hence high throughput with reasonable hardware\ncomplexity, representing a very competitive strategy\nwith regard to relevant state-of-the-art realizations.
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